1. Field of the Invention
This invention relates to static random access memories (SRAMs) and, more particularly, to techniques for replacement of a defective row in a SRAM with a redundant row.
2. Prior Art
If one or more memory cells in a row of a SRAM array are defective, the entire row is considered to be defective and must be replaced with a redundant row in the array. The prior art uses two techniques for replacement of a defective row in a SRAM. One such technique is called a xe2x80x9cshiftxe2x80x9d method and the other technique is called a xe2x80x9cbrute forcexe2x80x9d method.
FIG. 1 illustrates a typical global word line (GWL) control circuit 100 that is used to implement the prior art xe2x80x9cshiftxe2x80x9d method that provides one type of row redundancy for the word lines in a SRAM memory. For an exemplary SRAM with a total of 2048 word lines, four word lines (WLs) are grouped into one global word line (GWL) so that 512 GWLs are used for the SRAM with 2048 word lines. Each GWL then uses a 4:1 post-decode circuit to access each of the four WLs in a particular GWL. This shift technique uses a separate GWL control circuit 100 for each of the 512 GWLs. Each control circuit 100 uses one GWL fuse element 102 for each GWL, so that a total of 512 fuses are used for the 512 GWLs and the corresponding 2048 WLs.
The 512 separate GWL control circuits are arranged in a cascade arrangement of separate GWL control circuits, one for each GWL. When a fuse 102 for a particular GWL control circuit is blown, each control circuit beyond the defective row shifts all of the memory cells up one row in the SRAM memory array. All of the addressing accommodates this shifted arrangement. Each control circuit 100 has a FH terminal that is connected to a corresponding FL terminal of the next higher GWL control circuit. Each control circuit 100 also has a XDH terminal that is connected to a corresponding XDL terminal of the next higher GWL control circuit. For the bottommost GWL control circuit, XDEC, FL and XDL are connected to VSS, or ground. Predecode address signals A76, A54, A32, and A10 are all connected to VSS for the top GWL control circuit. Postdecode address signals XR[3:0] are provided to select one of four word lines WL associated with a GWL. Each of the output signals WL[3:0] activates one of the four WLs associated with a particular GWL.
There are several criteria for determining that a row in the SRAM is a defective row. A row is determined to be defective because it has a single bad bit, more than one bad bit, or the entire row is defective for some reason. An associated GWL fuse element 102 is blown for the defective row. This disables the GWL control circuit 100 and shifts the GWL control operation physically to a next GWL control circuit above. This shift continues up until the actual control circuit for the redundant GWL row is reached at the top of the rows of GWL control circuits.
An advantage of the shift method is that only one fuse needs to be to blown for the GWL control circuit of a defective memory row. However, an important disadvantage of the shift method is that it requires a fuse to be available for each GWL control circuit , so that, for example, 512 virgin fuses are required for the 512 GWL control circuits, even though only one fuse is to be blown. A further disadvantage is that this type of system is not flexible because only one defective memory row out of 512 memory rows can be replaced with this method.
For the shift technique, the decoder redundancy could be further subdivided by dividing the memory into several smaller memory blocks with a redundant GWL control circuit and a redundant memory row for each smaller memory block. For a memory with 512 GWL control circuits that is divided into four memory blocks, one redundant GWL control circuit is provided for every 128 GWLs. This still limits this technique to one redundant GWL for 128 GWLs. If the 128 GWL group had two bad GWLs, this technique would not work even though there may be three other unused redundant GWL control circuits and redundant memory rows provided for the other three 128-row groups.
FIG. 2 illustrates another redundancy control circuit 200 for providing row redundancy for a defective SRAM row. This circuit uses a so-called xe2x80x9cbrute forcexe2x80x9d technique because it disables all of the regular GWLs and activates a redundant GWL whenever an address for a defective row is detected. The input signals to the redundancy control circuit 200 are nine bits [A0:A8] of a nine-bit address signal. The output control signals of the redundancy control circuit 200 are a redundant GWL control signal REGWL and a RFLAG signal that turns off the regular GWLs. When the RFLAG signal goes to 0, it turns off all the regular GWLs and brings up the redundant GWL control signal REGWL. The defective redundancy control circuit 200 includes a fuse enable FENABLE circuit 202 and 9 fuse decoder circuits FRXDECFUSE circuits 204a-204i. 
FIG. 3 illustrates the FENABLE circuit 202. When it is not blown open, a fuse element 206 provides a VCC voltage to the drain terminal of a pull-down NMOS transistor 208 and to an input terminal of a first inverter 210. The Gate terminal of the pull-down NMOS transistor 208 is connected to the output terminal of the first inverter 210. The output terminal of the inverter 210 is connected to an input terminal of a second inverter 212. The output terminal of the second inverter 212 is connected to a NORMH output terminal 214 and to an input terminal of a third inverter 216, the output terminal of which is connected to a NORML terminal 218. When the fuse element 206 is blown open, the drain terminal of the pull-down transistor 208 is at a low voltage, which is inverted through the first inverter 210 to turn on the pull-down transistor 208. This provides a high signal at the NORMH terminal 214 and a low signal at the NORML terminal 218.
FIG. 4 illustrates a typical FRXDECFUSE circuit 204 that includes a transfer gate 250 that is controlled by the NORMH and NORML signals at terminals 252 and 254, respectfully. An AIB input terminal 256 to the transfer gate 250 is connected to the input terminal of the transfer gate 250 and to an input terminal of an inverter 258. An output terminal of the transfer gate 250 is connected through a fuse element 260 to an RAIB output terminal. An output terminal of the inverter 258 is connected through another fuse element 264 to the RAIB output terminal. When the RFLAG signal goes to 0, it turns off all the regular GWLs and brings up the redundant GWL signal REGWL.
An advantage of the brute force method is that it is very flexible. If setup for 4 redundant GWLs per 512 regular GWLs, you are not limited to just one redundant GWL per 128 GWL as in the shift method. This method could accommodate bad memory rows associated with 4 GWLs in a 128 GWL group. This method also requires less total virgin fuses because 19 fuses are required per redundant GWL. A disadvantages of this method is that 10 fuses need to be blown per redundant GWL. The requirement of 19 virgin fuses for each of the four redundant GWL is a disadvantage.
Consequently, a need exists for an SRAM with a more cost-effective, efficient technique for controlling a redundant row substituted for a defective row.
It is therefore an object of the invention to provide a fuse-controlled redundancy control system for a SRAM that, overall, uses fewer virgin fuses, which equates to less fuse area that provides a smaller chip size and a lower chip cost.
It is another object of the invention to provide a fuse-controlled redundancy control system for a SRAM that has fewer fuses to blow, which results in less time required for a laser to blow fuses and which proves for lower chip cost.
It is another object of the invention to provide a fuse-controlled redundancy control system for a SRAM that provides flexibility in designating redundant rows, which results in more die area saved and a lower chip cost.
In accordance with these and other objects of the invention, a fuse-controlled, row-redundancy control system for a SRAM is provided which includes a defective-row multi-bit storage array of static circuits, each of which static circuits is programmed to store one of the address bits of a predetermined defective row of the SRAM. Each of the static circuits includes a single fuse that is blown to indicate a first state of the one of the address bits and that is not blown to indicate a second state of the one address bit A comparator compares the address bits of the predetermined defective row of the SRAM with corresponding address bits of row-address signals that are received by the SRAM. The comparator includes a fuseless, exclusive logic circuit that compare individual bits of the row address signals received by the SRAM to corresponding ones of the address bits of the predetermined defective row of the SRAM. The comparator also provides a RFLAG control signal that indicates that the stored address bits of the defective row of the SRAM match the respective received row address bits for the SRAM. The RFLAG control signal also disables a word line corresponding to the defective row of the SRAM and enables a redundant SRAM word line for a redundant SRAM row so that a redundant SRAM row is substituted for the defective row of the SRAM.
The system further includes a decoder for decoding each global word line from one of the plurality of local word lines. The present invention is also applicable to a SRAM that does not use global word lines.
The fuseless exclusive-logic circuit also includes a preset control signal for initially enabling the comparator.
A method according to the present invention is provided for substituting a redundant row for a predetermined defective row of a SRAM. The method includes storing address bits of a defective row of the SRAM in an array of static circuits, where each of the static circuits includes a single fuse that is blown to indicate a first state of its respective address bit and that is not blown to indicate a second state of its respective address bit. Each of the stored address bits of the defective row of the SRAM is compared with a corresponding received row address bit for the SRAM to provide a RFLAG control signal that indicates that the stored address bits of the defective row of the SRAM match the respective received row address bits for the SRAM. When the RFLAG control signal is provided, a SRAM word line corresponding to the defective row of the SRAM is disabled and a redundant SRAM word line for a redundant SRAM row is enabled so that a redundant SRAM row is substituted for the defective row of the SRAM.